1. Field of the Invention
The present invention relates to a synchronous dynamic random access memory (synchronous DRAM or SDRAM) that operates synchronously with an externally-input signal. More particularly, this invention is concerned with a synchronous DRAM in which a signal path involved in one processing operation is divided into a plurality of stages of pipelines and the stages are operated in parallel in order to speed up processing.
2. Description of the Related Art
Normally, a signal is input externally to a semiconductor integrated circuit (including an LSI), a processing operation is carried out according to the input signal, and then an output signal is provided. It is therefore important to provide an output signal at a suitable timing relative to an external input signal. In the case of a general-purpose LSI, the timing is generally defined by the specifications for the LSI. Taking an SDRAM for instance, the timing of outputting data at a state-transition edge of an address signal and a data setup time required for writing data are specified together with a maximum frequency of the address signal.
In recent years, there has been an urgent need for an interface capable of operating quickly in an effort to cope with a high-frequency clock used by a CPU in a computer system or with high processing speeds of other various electronic circuits. For example, a CPU using a clock whose frequency is 100 MHz or higher has made its debut. An access speed or data transfer speed of a DRAM widely adopted as a main memory is one tenth of this clock frequency. Various novel types of DRAMs including an SDRAM have been proposed in an attempt to realize a data transfer speed of 100 MHz or higher.
An SDRAM inputs or outputs data synchronously with an externally-input high-frequency clock. SDRAMs can be of a type which includes a plurality of units capable of inputting or outputting data of a plurality of bits in parallel and in which an external interface is speeded up by converting the data of a plurality of bits into serial data, and a type in which internal operations are pipelined and the operations of pipelines are carried out in parallel in order to thus speed up processing. The present invention relates to a pipelined SDRAM. Herein, the pipelined SDRAM shall be referred to simply as an SDRAM.
The SDRAM can input or output data of consecutive addresses, that is, consecutive column addresses at a high speed. This operation mode is called a burst mode. For inputting or outputting data in the burst mode, a control signal indicating the burst mode is input. In addition, an address at which input or output is started and the lengths of data items to be input or output consecutively are input. In the SDRAM adopting pipelining, a signal path to be involved in input or output of data in the burst mode or, in reality, an output path along which data is read, is pipelined.
A processing circuit in an SDRAM to be involved in a read operation is divided into a plurality of stages along the flow of processing. The division circuits on the respective stages are called pipelines. A gate for controlling the timing of inputting data of a previous stage to a subsequent stage is interposed between pipelines of adjoining stages. An internal clock is supplied from a clock buffer to the pipelines and gates. The pipelines and gates are controlled according to the supplied internal clock.
In recent years, there has been a demand for a higher operation speed in the field of battery-driven portable computers. The use of an SDRAM as a memory device is demanded. In a battery-driven portable computer, it is very important to minimize power consumption. Specifically, the SDRAM must minimize a power consumption thereof while operating quickly.
A gate in the SDRAM is formed with a transfer gate composed of a p-channel transistor and n-channel transistor. The transfer gate repeats an on-off operation at a high speed and therefore suffers from a very high power consumption (charging current and discharged current). This leads to a large power consumption of a whole SDRAM. Even if the demand for fast operation is met, there arises a problem that the demand for low power consumption cannot be met.